2.5GHz, +20dBm Power Amplifier IC
in UCSP Package
RF Input
The internal input stage impedance matching network
is integrated on the MAX2240, so it is possible to
directly connect a 50 Ω transmission line to RFIN. No
external matching is required.
Output Stage (RF Output)
The output stage of the MAX2240 power amplifier is the
collector of a transistor. The DC bias and impedance
matching network are off-chip as shown in the Typical
Application Circuit.
An off-chip external network, as with most PA ICs, is
used to achieve higher efficiency and output power
than is typically achieved using low-Q on-chip match-
ing elements. Optimum output power and efficiency are
achieved with a particular impedance on the output at
the operating frequencies of interest and a short at the
RF harmonic frequencies. This impedance is specified
relative to a reference plane at the amplifier output into
the matching network and load. This is the impedance
that achieves the output power and current consump-
tion listed in the electrical specifications. It is shown
below in the chart and table of Figure 1.
MATCHING IMPEDANCE FOR RF OUT PIN
SMITH CHART
2
1
1: (15.5 Ω + J16.7 Ω ), 2.4GHz
2: (15.0 Ω + 19.0 Ω ), 2.5GHz
MATCHING IMPEDANCE
is a lowpass network formed by the series transmission
line section T1 and the open-stub transmission line sec-
tion T2. The transmission line network acts like a series
inductance and shunt capacitance. T1 and T2 are
expressed as electrical lengths of a particular charac-
teristic impedance line, but could be designed with dif-
ferent impedance lines.
Choose the length of T2 to provide a short at the 2nd
harmonic frequency of the fundamental, and significantly
attenuate its amplitude at the output—1/4 wave at the
2nd harmonic frequency of 4.9GHz. The 3rd harmonic is
attenuated through the clever use of the parasitic capac-
itance in the choke. This capacitance rolls off the choke
impedance at higher frequencies and appears as a
low impedance at the 3rd harmonic frequency.
The output series capacitor is used as a DC-blocking
capacitor and a final matching element. A value of
10pF is recommended.
As explained in the Power-Supply Considerations sec-
tion, for proper DC biasing, the PA requires a connection
to V CC through an inductor, serving as a choke. Locate
the inductor on the load side of transmission line T1. The
recommended inductor value is 22nH. However, its
value is not critical but must provide an impedance that
is several hundred ohms. Choose an inductor with a self-
resonant frequency at or slightly below 2.4GHz. The
inductor Q is not critical; a moderate Q (>25) is suffi-
cient. Remember to provide sufficient current-handling
capability for the inductor, in this case at least 200mA.
Also, a 220pF bypass capacitor is recommended at the
supply voltage end of the inductor.
Layout
Design the layout for the PA IC to be as compact as
possible to minimize the magnitude of parasitics. The
chipscale IC package uses a bump pitch of 0.5mm (19.7
mil) and bump diameter of 0.3mm (~12 mil). Therefore,
lay out the solder pad spacing on 0.5mm (19.7 mil) cen-
ters, use a pad size of 0.25mm (~10 mil) and a solder
mask opening of 0.33mm (13 mil). Round or square
pads are permissible. (Refer to the Maxim document,
Wafer Level Ultra-Chipscale Packaging for additional
detailed information on UCSP layout and handling.)
Connect multiple vias from the ground plane as close to
FREQUENCY
(GHz)
2.4
2.45
2.5
R
15.5
15.2
15.0
X
16.7
17.9
19.0
| Γ |
0.57
0.58
0.59
< Γ
140
138
136
the ground pins as possible.
As already described, locate the capacitors as close as
possible to the IC supply voltage pin or supply end of
the series inductor. Place the ground end of these
capacitors near the IC GND pins to provide a low-
impedance return path for the signal current.
Figure 1. Output Impedance
The primary power-matching structure
_______________________________________________________________________________________
7
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